Person

DM368在內頻上提升到432MHZ,相對於DM365其它功能部分幾乎一樣.唯一最大的改變就是能夠支持1080P的H.264壓縮.IPCAM裡算是很不錯的規格了.不過沒有de-interlace使得在使用tv-decoder會有interlace問題.而Hi3515/3520雖然有de-interlace,但是H.264壓縮規格似乎只到1280x1024的輸出..難道就沒有比較兩全其美的方案嗎?

回歸正題, 過去接觸的平台,硬體初始化都在bootloader做比較多,TI有一個簡單的UBL設計,讓硬體的初始化是在這個比較小的Firmware上做, 然後完成之後,才進到真正的bootloader.

RBL -> UBL -> Bootloader -> Kernel

所以input crystal不變的情況下,幾乎不必改動到bootloader or kernel的程式碼.理論上只要修正UBL的區段即可.

以下是比較365和368不同的PLL registerg設定:

diff -r flash_utils_dm365/DM36x/Common/src/device.c flash_utils_dm368/DM36x/Common/src/device.c
366,367c366,367
<       PLL1->PLLM = 90; //# VCO will 24*2M/N+1 = 540Mhz
<       PLL1->PREDIV = (0x8000|0x7);
---
>       PLL1->PLLM = 170; //# VCO will 24*2M/N+1 = 680Mhz
>       PLL1->PREDIV = (0x8000|0xB);
379,383c379,383
<       PLL1->PLLDIV3 = 0x8001;   // POST DIV 540/(1+1)  -> MJCP/HDVICP (270MHz)
<       PLL1->PLLDIV4 = 0x8003;   // POST DIV 540/(3+1)  -> EDMA CFG (135MHz)
<       PLL1->PLLDIV5 = 0x8001;   // POST DIV 540/(1+1)  -> VPSS
<       PLL1->PLLDIV6 = 0x8013;   // POST DIV 540/(19+1) -> 27MHz VENC
<       PLL1->PLLDIV7 = 0x8000;   // POST DIV 540                -> DDR(270MHz)
---
>       PLL1->PLLDIV3 = 0x8001;   // POST DIV 680/(1+1)  -> MJCP/HDVICP (340MHz)
>       PLL1->PLLDIV4 = 0x8003;   // POST DIV 680/(3+1)  -> PERI_CFG(should be MJCP/2,170)
>       PLL1->PLLDIV5 = 0x8001;   // POST DIV 680/(1+1)  -> VPSS (340)
>       PLL1->PLLDIV6 = 0x8018;   // POST DIV 680/(24+1) -> 27.2MHz VENC
>       PLL1->PLLDIV7 = 0x8000;   // POST DIV 680            -> DDR(680MHz)
385,386c385,386
<       PLL1->PLLDIV8 = 0x800A;   // POST DIV 540/(10+1) -> MMC0/SD0(49.09MHz)
<       PLL1->PLLDIV9 = 0x8001;   // POST DIV 540/2      -> CLKOUT
---
>       PLL1->PLLDIV8 = 0x800D;   // POST DIV 680/(13+1) -> MMC0/SD0(48.5MHz)
>       PLL1->PLLDIV9 = 0x8001;   // POST DIV 680/2      -> CLKOUT
438,439c438,439
<       PLL2->PLLM = 99;
<       PLL2->PREDIV = 0x8000|0x7; //# VCO will be 24*2*PLLM/PREDIV+1 = 594MHz
---
>       PLL2->PLLM = 144;
>       PLL2->PREDIV = 0x8000|0x7; //# VCO will be 24*2*PLLM/PREDIV+1 = 864MHz
447,449c447,449
<       PLL2->PLLDIV2 = 0x8001;          // POST DIV 594/(1+1)  -> ARM (297 MHz)
<       PLL2->PLLDIV4 = 0x801C;      // POST DIV 594/(28+1) = 20.48  -> VOICE Codec Clock
<       PLL2->PLLDIV5 = 0x8015;      // POST DIV 594/(21+1) 27 -> VIDEO
---
>       PLL2->PLLDIV2 = 0x8001;          // POST DIV 864/(1+1)  = 432 -> ARM
>       PLL2->PLLDIV4 = 0x8029;      // POST DIV 864/(41+1) = 20.57 -> VOICE Codec Clock
>       PLL2->PLLDIV5 = 0x801F;      // POST DIV 864/(31+1) = 27 -> VIDEO
523,525c523,525
<       DDR->SDTIMR  = 0x45246412;              //Program SDRAM Timing Control Register1
<       DDR->SDTIMR2 = 0x3A25C742;              //Program SDRAM Timing Control Register2
---
>       DDR->SDTIMR  = 0x5525745B;              //Program SDRAM Timing Control Register1
>       DDR->SDTIMR2 = 0x442EC863;              //Program SDRAM Timing Control Register2
538,539c538,539
<       DDR->SDRCR = 0x0000083A;                //SDRAM Refresh(270MHz*7.8 = 2106)
---
>       DDR->SDRCR = 0x00000A5C;                //SDRAM Refresh(340MHz*7.8 = 2652)
555,557c555,557
<       AEMIF->A1CR = 0x4820230C;
---
>       AEMIF->A1CR = 0x5030420C;

以上是某家的參考值.但我自己的案例是用原始的UBL source code. 所以針對PLL1/PLL2調整之後,再調整DDR2,EMIF的參數即可.

跑出來的BogoMIPS:215,原來只有148左右.

//Program the Multiper and Pre-Divider for PLL1
PLL1->PLLM   =   170;   // VCO will 24*2M/N+1 = 680Mhz
PLL1->PREDIV =   0x8000|0xB; 

//Program the PostDiv for PLL1
PLL1->POSTDIV = 0x8000;

// Post divider setting for PLL1 
PLL1->PLLDIV2 = 0x8001;   // not used.
PLL1->PLLDIV3 = 0x8001;   // POST DIV 680/(1+1)  -> MJCP/HDVICP (340MHz)
PLL1->PLLDIV4 = 0x8003;   // POST DIV 680/(3+1)  -> PERI_CFG(should be MJCP/2,170)
PLL1->PLLDIV5 = 0x8001;   // POST DIV 680/(1+1)  -> VPSS (340)
PLL1->PLLDIV6 = 0x8018;   // POST DIV 680/(24+1) -> 27.2MHz VENC
PLL1->PLLDIV7 = 0x8000;   // POST DIV 680      -> DDR(680MHz)
PLL1->PLLDIV8 = 0x800D;   // POST DIV 680/(13+1) -> MMC0/SD0(48.5MHz)
PLL1->PLLDIV9 = 0x8001;   // POST DIV 680/2       -> CLKOUT

//Program the Multiper and Pre-Divider for PLL2
PLL2->PLLM   =   144;   // VCO will 24*2M/N+1 = 594Mhz

PLL2->PREDIV = 0x8000|0x7; //# VCO will be 24*2*PLLM/PREDIV+1 = 864MHz
PLL2->POSTDIV = 0x8000;

PLL2->PLLDIV2 = 0x8001;        // POST DIV 864/(1+1)  = 432 -> ARM
PLL2->PLLDIV4 = 0x8029;      // POST DIV 864/(41+1) = 20.57 -> VOICE Codec Clock
PLL2->PLLDIV5 = 0x801F;      // POST DIV 864/(31+1) = 27 -> VIDEO

DDR->DDRPHYCR = 0x000000C6;
DDR->SDBCR = 0x08D34A32;        //Program SDRAM Bank Config Register
DDR->SDBCR = 0x0853CA32;
DDR->SDTIMR  = 0x5525745B;        //Program SDRAM Timing Control Register1
DDR->SDTIMR2 = 0x442EC863;        //Program SDRAM Timing Control Register2
DDR->PBBPR = 0x000000FE;
DDR->SDBCR = 0x08534A32;        //Program SDRAM Bank Config Register
DDR->SDRCR = 0x00000A5C;        //SDRAM Refresh(340MHz*7.8 = 2652)

AEMIF->AWCCR = 0xff;
AEMIF->A1CR = 0x5030420C;
AEMIF->NANDFCR |= 1;

實際output:

PLL0: fixedrate: 24000000, commonrate: 170000000, vpssrate: 340000000

PLL0: vencrate_sd: 27200000, ddrrate: 340000000 mmcsdrate: 48571428

PLL1: armrate: 432000000, voicerate: 86400000, vencrate_hd: 27000000